Most general-purpose digital computers provide a system for detecting and handling single-bit or multiple-bit parity errors. The occurrence of soft errors is not uncommon when data signals are being read from storage devices such as static random access memories (SRAMs) and dynamic random access memories (DRAMs). This is especially true when high-density memories are employed, as is generally the case in large data processing systems.
In one example, the presence of alpha and other particles can cause soft parity errors in static random access memories (SRAMs) and dynamic random access memories (DRAMs). Alpha particles are randomly generated, positively charged nuclear particles originating from several sources, including cosmic rays that come from outer space and constantly bombard the earth, and from the decay of natural occurring radioisotopes like Radon, Thorium, and Uranium. Concrete buildings, and lead based products such as solder, paint, ceramics, and some plastics are all well-known alpha emitters. Especially smaller geometry storage devices can be adversely affected by the emission of alpha and other particles, causing a higher occurrence of soft parity errors.
As discussed above, storage devices such as any type of RAM are susceptible to the types of error conditions discussed above. This includes Instruction Cache RAMs and Operand Cache RAMs, which are commonly used in many data processing systems. For example, to increase system performance, it is common to use one or more Instruction Cache RAMs to cache one or more instructions for selection and execution by an instruction processor. Typically, if the desired instruction is not present in the Instruction Cache RAM, a cache miss occurs, and the desired instruction must be read from a higher level memory, such as a second level cache memory. Likewise, it is common to provide one or more Operand Cache RAMs to cache one or more operands for use by instructions that are executed by the instruction processor. If the desired operand is not present in the Operand Cache RAM, a cache miss occurs, and the desired operand must typically be read from a higher level memory, such as a second level cache memory.
When a parity error occurs in an Instruction Cache RAMs or an Operand Cache RAM, system performance and reliability can be affected. One way to detect parity errors is through the use of parity bits, as is known in the art. In some cases, a detected error is reported to a maintenance processor, operating system, or other error-handling system, which in the case of an Instruction Cache RAM or an Operand Cache RAM, often results in a critical error that halts the execution of the data processing system, and often requires a specialized operating system routine, or in some cases a maintenance technician, to help diagnose and fix the problem. This can bring the system down for some time, which can result in inefficient use of the data processing system resource. What is needed, therefore, is an improved system and method for detecting and then recovering from errors in an Instruction Cache RAM and/or an Operand Cache RAM.